Carrier mobility in a metal oxide semiconductor field effect transistor (MOSFET) may be manipulated by a stress applied to the channel of the MOSFET. Even relatively small changes in the stress of the channel may result in large changes in carrier mobility for some combinations of semiconductor material and crystallographic orientations, and may be utilizes to increase the transconductance (or reduced serial resistance) of the MOSFET, thereby enhancing the performance of the MOSFET.
When stress is applied to the channel of a semiconductor transistor, the applied stress and the resulting strain on the semiconductor structure within the channel affects the band gap structure (i.e., breaks the degeneracy of the band structure) and changes the effective mass of carriers. The effect of the stress depends on the crystallographic orientation of the plane of the channel, the direction of the channel within the crystallographic orientation, and the direction of the applied stress. Under stress applied the channel of the MOSFET, the mobility of carriers, and as a consequence, the transconductance and the on-current of the transistor are altered from their original values for an unstressed semiconductor.
The effect of uniaxial stress, i.e., a stress applied along one crystallographic orientation, on the performance of semiconductor devices, especially on the performance of a MOSFET (or a “FET” in short) devices built on a silicon substrate, has been extensively studied in the semiconductor industry. For a p-type MOSFET, i.e., a PMOSFET (or a “PFET” in short) that utilizes a silicon channel or silicon-germanium alloy channel, the mobility of minority carriers in the channel (which are holes in this case) increases under longitudinal compressive stress along the direction of the channel, i.e., the direction of the movement of holes or the direction connecting the drain to the source. Conversely, for an n-type MOSFET, i.e., an NMOSFET (or an “NFET” in short) that utilizes a silicon channel or a silicon-germanium alloy channel, the mobility of minority carriers in the channel (which are electrons in this case) increases under longitudinal tensile stress along the direction of the channel, i.e., the direction of the movement of electrons or the direction connecting the drain to the source. These opposite requirements for the type of stress for enhancing carrier mobility between the PMOSFETs and NMOSFETs have led to prior art methods for applying at least two different types of stress to the semiconductor devices on the same integrated chip.
While such beneficial effects of stress are known in the art, a difficulty arises since two different types of field effect transistors require two different types of stress. Specifically, a longitudinal compressive stress is required or a PMOSFET, and a longitudinal tensile stress is required for an NMOSFET. For a semiconductor circuit employing field effect transistors having a silicon-germanium alloy channel, two separate mechanisms are needed to generate the two opposite types of stress in the channel for PMOSFETs and NMOSFETs.
With scaling down of the critical dimension, it becomes more and more difficult to apply strong stress in both NFET and PFET channel with stress liners. The stress enhancement of embedded source/drain can be used to main device performance with changing lattice constant or fraction of chemical composition in an embedded source and/or an embedded drain.
In view of the above, there exists a need for a semiconductor structure providing a longitudinal compressive stress to a p-type MOSFET having a silicon-germanium alloy channel, while providing a longitudinal stress to an n-type MOSFET having a silicon-germanium alloy channel, and methods of manufacturing the same.